You need a combinational logic with 16 input pins, 4 select lines, and one output. In a 4:1 mux, you have 4 input pins, two select lines, and one output. At least you have to use 4 4:1 MUX, to obtain 16 input lines. But you then have a logic with 4 output pins. We can use another 4:1 MUX, to multiplex only one of those 4 outputs at a time.
module mux4to1_gate(out,in,sel);
input [0:3] in;
4x1 mux verilog Search and download 4x1 mux verilog open source project / source codes from CodeForge.com. SOPC technology using verilog create Hello program. Hey here is a ise format code for xilinx software verilog 8 bit fixed point coding use this for example for coding with test bench. Download(s) 1421. Jan 26, 2013 - MUX 4 bit Module module mux4bit(a, s, o); input 3:0 a; input 1:0 s; output o; reg o; always @(a or s) begin case (s) 2'b00:o=a0; 2'b01:o=a1;.
input [0:1] sel;
output out;
wire a,b,c,d,n1,n2,a1,a2,a3,a4;
not n(n1,sel[1]);
not nn(n2,sel[0]);
and (a1,in[0],n1,n2);
and (a2,in[1],n2,sel[1]);
and (a3,in[2],sel[0],n1);
and (a4,in[3],sel[0],sel[1]);
or or1(out,a1,a2,a3,a4);
endmodule
HDL Program File for 16:1 MUX [ MUX16X1.v
module mux16to1(out,in,sel);
input [0:15] in;
input [0:3] sel;
output out;
wire [0:3] ma;
mux4to1_gate mux1(ma[0],in[0:3],sel[2:3]);
mux4to1_gate mux2(ma[1],in[4:7],sel[2:3]);
mux4to1_gate mux3(ma[2],in[8:11],sel[2:3]);
mux4to1_gate mux4(ma[3],in[12:15],sel[2:3]);
mux4to1_gate mux5(out,ma,sel[0:1]);
endmodule
module testmux_16;
reg [0:15] in;
reg [0:3] sel;
wire out;
mux16to1 mux(out,in,sel);
initial
begin
$monitor('in=%b | sel=%b | out=%b',
in,sel,out);
end
initial
begin
in=16'b1000000000000000; sel=4'b0000;
#30 in=16'b0100000000000000; sel=4'b0001;
#30 in=16'b0010000000000000; sel=4'b0010;
#30 in=16'b0001000000000000; sel=4'b0011;
#30 in=16'b0000100000000000; sel=4'b0100;
#30 in=16'b0000010000000000; sel=4'b0101;
#30 in=16'b0000001000000000; sel=4'b0110;
#30 in=16'b0000000100000000; sel=4'b0111;
#30 in=16'b0000000010000000; sel=4'b1000;
#30 in=16'b0000000001000000; sel=4'b1001;
#30 in=16'b0000000000100000; sel=4'b1010;
#30 in=16'b0000000000010000; sel=4'b1011;
#30 in=16'b0000000000001000; sel=4'b1100;
#30 in=16'b0000000000000100; sel=4'b1101;
#30 in=16'b0000000000000010; sel=4'b1110;
#30 in=16'b0000000000000001; sel=4'b1111;
end
endmodule
I'm trying to learn VHDL through P. Ashenden's book: Designer's Guide to VHDL. Chapter one's exercise 10 asks you to write 2-to-1 (I'm assuming 1 bit wide) MUX in VHDL and simulate it. I apologize in advance for being a complete noob. This is my first VHDL code.
My MUX didn't produce any errors or warnings in synthesis. My test bench doesn't produce errors or warnings, either. However, the simulation comes up completely blank, except for the names of the signals.
I've tried looking at a multitude of other MUX examples online (as well as a bench test example from the book), all of which gave errors when I tried sythesizing them, so I wasn't confident enough to use them as guides and didn't get much out of them. I'm not sure what I'm doing wrong here. I'd include an image of the simulation, but I don't have enough rep points :(
Also, I realize that a good MUX should also have cases for when it receives no select input/high impedance values, ect.. In this case, I'm just trying to get the toy model working.
The MUX code is:
The test bench code is:
SamDawgSamDawg
1 Answer
You don't need a use clause for package std_logic_1164 when using type bit (declared in package standard).
Your process statement
choose
in MUXtop has no sensitivity clause which cause the process to continually execute in simulation. (It won't do anything until you trip over a delta cycle iteration limit which might be set to infinity).I added a sensitivity list, commented out the superfluous use clauses in the two design units and added some more stimulus steps as well as a final
wait for 10 ns;
to allow the last action to be seen in your testbench:And that gives:
(clickable)
user1155120user1155120